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PA-RISC Machine Instructions

PA-RISC machines use an instruction set that is based on 32 general-purpose registers. You see machine code on the screen when you use the Debugger on MPE, both in the dc command that dumps code and the won command that turns "Windows On."

Text version.

Assembler Code Explanation
LDIL$2000,8R8:=$2000
LDO32(8),8R8:=R8 + 32
LDW-12(0,5),21R21:=memory(R5-12)
STH8,0, (0,21)memory(R21):=R8
LDH-8(0,5),22R22:=memory(R5-8)
EXTRS22,31,16,22R22:=sign-extended(R22)
LDO-1(22),22R22:=R22 - 1

Expect to find the instruction source on the left and the destination on the right:

Text version.

LDWd(s,b),t
STHr,d(s,b)
LDd(b),t
LDILi,t
EXTRSr,p,len,t

where

d=displacement
t=target register
i=immediate value
s=space id
r=source register
p=bit position
b=base register
(s,b)=memory address
len=number of bits

In Load and Store instructions you see (0,xx) for the memory address, where 0 is the Space Id and xx is the Base Register. Space Id 0 is a special case, see Space Registers. The best instruction summary is the Precision Architecture and Instruction Reference Card (09740-90014).

Here are some tips to help you guess the function of an instruction from the mnemonic:

Text version

Arithmetic:ADD@and SUB@.
Branches:B@ as in BL Branch and Link, BV Branch Vectored.
Compare and Branch:C@ as in COMIBF, COMpare Immediate and Branch If False.
Extract:EXTRS for signed and EXTRU for unsigned.
Load:L@ as in LDH load halfword, LDO load offset.
Shift:SH@ as in SH2ADD Shift 2 and Add.
Store:ST@ as in STB Store Byte, STW Store Word.

A series of ADD@ and SH# ADD instructions, is usually a multiply operation without a multiply instruction. Because of delayed branches, the instruction after a branch is executed before the branch takes effect.


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